Course # ECE 40001 Ken Arnold rev 7/24/05 KA
In
general, the project consists of a microprocessor or microcontroller with
external memory and I/O. The choice of
the processor is up to the student, but it must be a part from the same family
of CPUs used as an example in the course (an 8051 derivative with external
memory and I/O). The processor chosen
should be consistent with the resources you have available to you. While there is no minimum time requirement,
a typical project will probably take somewhere between 50 and 60 hours to
complete. The time you will need
depends on your skill level and the complexity of the project you choose. Please recognize that this project will be a
design for the core part of a micro, but will not include any useful I/O. The processor design includes only the core
elements: CPU, program memory, data memory, and some memory mapped I/O (I/O
that appears in the 8051’s external data memory address space). If you are interested in designing your
project for expansion to a practical application, you may want to define the
design of the overall system, and just implement the core elements for this
project. Please be aware that only the
core part of the design will be graded, and any time spent on additional tasks
will not affect or improve your grade.
The block diagram in figures 6-1 and 7-7 of the Embedded Controller
Design text are representative of what you will design. In this project, emphasis is placed on worst
case design and analysis of the hardware.
10
pts. 1) Proposal due Week 4
100
pts. 2) Draft due Week 7
100
pts. 3) Final Report due on the
last class meeting
The
project accounts for just over half of the total possible course grade (210/410
total).
8 bit 8051 family microprocessor or
microcontroller with external bus
EPROM memory or equivalent for
non-volatile program storage
Static RAM memory for data storage
Memory mapped Input port (e.g. read
DIP switch inputs)
Memory mapped Output port (e.g.
illuminate some LEDs)
Control/address decode logic designs
in two versions:
1) Discrete gates and
decoders
2) Programmable Logic
Device (PLD) implementation
The
processor you choose MUST be configured to fetch and execute programs
and data from memory EXTERNAL to the CPU chip, and must include memory
mapped I/O. Otherwise, you could turn in a single chip
design, which wouldn't be much of a challenge!
The
design can, and probably should change as you progress, and your reports should
reflect this.
Each
submission builds upon the previous one: Proposal, Draft and Final Reports.
The
Proposal phase is intended to define WHAT you will be doing for your project,
what resources you can to commit to it, and how many hours you are planning to
spend to complete it. You should state
what processor you plan to use. A block
diagram should be included if you have a specific application in mind. The purpose of the time estimate is to allow
me to evaluate your estimate and the project complexity in view of your
experience and resources so that I can advise you about the scope of your project.
Description
List available resources, equipment,
and your experience
Time estimated to complete, in hours
The
Draft is intended to describe HOW your design will be implemented. It should contain ALL information submitted
in the proposal, updated as needed. The
Draft should define your initial design with a block diagram or preliminary
schematic to the chip level (does not need pin numbers, etc., just functional
data), preliminary loading and timing analyses, and a project status
update. Additional information on the
CPU and other components to be used in the design should be included in the
draft. The control logic should be designed
two ways: using discrete logic decoders or gates, and using programmable logic
device(s). The hardware can be
implemented in either way if you build the project.
Proposal material above, updated as
required
Detailed Block Diagram
Preliminary schematic
Preliminary memory map
Key timing diagrams
Samples of the loading, timing, and
noise margin analysis
Hours estimated vs. actual hours
spent to date
The
Final report is intended to PROVE that your design is correct, and document it
in detail sufficient to fabricate the hardware. It should contain ALL information submitted in the proposal and
draft phases, updated as necessary. The
final schematics should show all connections, accompanied by a bill of
materials specifying complete part numbers of ICs. The design should be documented in sufficient detail that a
technician could build it given only the report data.
Final
Report contents:
ALL Proposal
and Draft material above, updated and completed as required
Bill of Materials
Additional design of control and decode
logic using PLDs (Programmable
Logic Devices)
Timing diagrams as required to
support timing analysis
Detailed Analyses:
1)
Loading
(DC & AC)
2)
Noise
margin
3)
Timing
analysis computations
Hours estimated vs. actual hours
spent to date
What problems you had or what you
would do differently next time