;                             FILE SIGGEN1.ASM
;
;            Sample Program Demonstrating Two Signal Generating
;            Clocks Using Timers 0 and 1 in MODE 1. This Program
;            switches Port 1.0 and 1.1 using Timers 0 and 1.
;
;            The output frequency is adjusted by signalling the external
;            interrupt lines 1 and 2 for output1 and output 2.

;            NOTE: Mode 1 is the 16 Bit Manual Reload Mode.
;
;                     Written By S.C.T.  1/20/99


  $MOD52                        ; Include 8052 Definitions

  Timer0Low     EQU    7Fh     ; Create Timer Reload Variables
  Timer0High    EQU    7Eh

  Timer1Low     EQU    7Dh
  Timer1High    EQU    7Ch

  Output1       EQU     P1.2    ; Define the two outputs
  Output2       EQU     P1.3

;  ORG  4000h                   ; Start Program at SDK Code Space Base

  CLR   EA                      ; Disable Global Interrupts
  MOV   TMOD, #11h              ; Set Timers 0 and 1 to Mode 1

  MOV   Timer0Low,  #00h        ; Initialize Timer Variables
  MOV   Timer0High, #00h
  MOV   Timer1Low,  #00h
  MOV   Timer1High, #00h
                                
  MOV   TL0, Timer0Low          ; Reset Timer Registers
  MOV   TH0, Timer0High
  MOV   TL1, Timer1Low
  MOV   TH1, Timer1High

  CLR   TF0                     ; Clear Timer 0 Overflow flag
  CLR   TF1                     ; Clear Timer 1 Overflow flag
  CLR   Output1                 ; Clear Output Signal Ports
  CLR   Output2                    

  SETB  TR0                     ; Start Timer 0
  SETB  TR1                     ; Start Timer 1

loop1:
  JB    TF0,restart0            ; Go to Timer 0 Restart Routine
  JB    TF1,restart1            ; Go to Timer 1 Restart Routine
  JMP   loop1                   ; repeat loop until bit set

restart0:
  CLR   TR0                     ; Stop Timer 0
  CPL   Output1                 ; Complement Output 1 Bit
  CLR   TF0                     ; Clear Timer 0 Overflow
  MOV   TL0, Timer0Low          ; Reload Timer Registers
  MOV   TH0, Timer0High
  SETB  TR0                     ; Restart Timer 0
  JMP   loop1                   ; Go back to main loop

restart1:
  CLR   TR1                     ; Stop Timer 1
  CPL   Output2                 ; Complement Output Bit
  CLR   TF1                     ; Clear Timer 1 Overflow
  MOV   TL0, Timer0Low          ; Reload Timer Registers
  MOV   TH0, Timer0High
  SETB  TR1                     ; Restart Timer 1
  JMP   loop1                   ; Go back to main loop

  END
